Generally, in order to improve the burst error correcting capability of an optical disk player at the time of reproduction, the recorded data is interleaved and recorded on a disk after encoding the error correction. When reproduction is desired, the data read from the disk is de-interleaved and reproduced after decoding the error correction. In such de-interleaving and error correction decoding processes, the data is written to or read from memory in a predetermined block unit of signal processing.
FIG. 1 shows a process for error correction decoding of a conventional optical disk player. The data read from the disk is first demodulated and is then de-interleaved by a predetermined rule in a first de-interleave block 10 so that a first error correction is achieved in C1 error correction block 12. Any data errors which are not corrected by the first error correction are marked with a pointer C1. After again de-interleaving the data following C1 error correction in a second de-interleave block 14 by a predetermined rule, a second error correction is performed in C2 error correction block 16. The data which is not corrected by the C2 error correction is marked with a pointer C2 and de-interleaved at a third de-interleave block 18 by a predetermined rule. Finally, the data is output. The aforementioned de-interleaving operations are performed by writing the input data into predetermined block units, mainly using a random access memory (RAM), and regulating the read addressing. Usually, the RAM is associated with an 8-bit data bus.
Referring to FIG. 2, the conventional error correcting memory device has an address generating unit 20 and an error correcting memory 40. The address generating unit 20 consists of a first offset address generator 22 for writing the eight-to-fourteen (EFM) demodulated data, a second offset address generator 24 for reading the decoder output data and the pointer, a third offset address generator 26 for writing and reading during the error correcting process, a multiplexer 28 for selecting the output from first through third offset address generators, a base counter 30 for counting the present base and an adder 32 for generating a final address signal by adding the outputs from the base counter 30 and the multiplexer 28. The error correcting memory 40 writes or reads data and pointers through the data bus in the process of error correction decoding. Accordingly, since the data input to or output from the error correcting memory 40 in the conventional device, consists of one byte, that is to say, an eight bit unit, while the pointer consists of one bit, the data which is not corrected is marked with a 1-bit pointer, thereby occupying two words (two bytes) of memory. Therefore, out of two byte space formed by one byte of 8-bit data and one byte of a 1-bit pointer, seven bits remain empty and unused, which means an unnecessary increase in RAM size.
The present invention was motivated by a desire to solve the existing problems noted in conventional error correcting memory devices